-----------------------------
-- AND gate
-----------------------------

library ieee;
use ieee.std_logic_1164.all;

-----------------------------

entity AND_ent is
port(
	x: in std_logic;
	y: in std_logic;
	z: out std_logic
);
end AND_ent

-----------------------------

architecture AND_arch of AND_ent is
begin
	process(x, y)
	begin
   		-- compare to the truth table
		if ((x='1') and (y='1')) then
			z <= '1';
		else
			z <= '0';
		end if;
	end process;
end AND_arch;

architecture AND_beh of AND_ent is
begin
	z <= x and y;
end AND_beh;

-----------------------------
